Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit
Document Type
Article
Publication Date
1997
Publisher
IOP Publishing
Abstract
We have observed a unique phenomenon during low-gate voltage (V G) static stressing of metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Static stressing has been performed by probing n-MOSFET devices that are discrete, as well as devices that are embedded in a circuit. Although the measured substrate current for the circuit and discrete devices is similar, significantly more hole trapping is observed under low-V G static stressing of circuit devices. It is clear that the extent of hole trapping is circuit dependent, and that in actual operation the devices will not undergo such static stressing. Nevertheless, these devices provided a unique opportunity to study the role of hole trapping in interface-state formation. Thus, rather than identifying the cause for increased hole trapping, we focused our efforts on understanding the mechanisms of interface-state formation. It is found that while both electrons and holes are needed for the formation of interface states, it is hole trapping that is the rate-limiting factor in device degradation.
Recommended Citation
A. Gupta, D.S. Sugiharto, C.Y. Yang, N. Matsuzaki, M. Minami, T. Yamanaka, and T. Nagano, “Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit,” Japanese Journal of Applied Physics 36, 4272-4277 (1997).
