PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

Authors

C-N Ni
Y-C Huang
S Jun
S Sun
Anshul A. Vyas, Santa Clara UniversityFollow
F Khaja
KV Rao
S Sharma
N. Breil
M. Jin
C. Lazik
A. Mayur
J. Gelatos
H. Chung
R. Hung
M. Chudzik
N. Yoshida
N. Kim

Document Type

Conference Proceeding

Publication Date

5-30-2016

Publisher

IEEE

Abstract

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e^-8 to 2.8e^-9 Ωcm² , due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact

Comments

International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)
25-27 April 2016
Hsinchu, Taiwan

Recommended Citation

Ni, C.-N., Huang, Y.-C., Jun, S., Sun, S., Vyas, A., Khaja, F., Rao, K. V., Sharma, S., Breil, N., Jin, M., Lazik, C., Mayur, A., Gelatos, J., Chung, H., Hung, R., Chudzik, M., Yoshida, N., & Kim, N. (2016). PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond. 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 1–2. https://doi.org/10.1109/VLSI-TSA.2016.7480531