Date of Award

7-2017

Document Type

Thesis - SCU Access Only

Publisher

Santa Clara : Santa Clara University, 2017.

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical Engineering

First Advisor

Tokunbo Ogunfunmi

Abstract

Nowadays, mobile systems can be used as a video stream transmitter as well as receiver. That is, mobile systems can send a movie with high resolution as a transmitter and a TV or monitor can display the movie on the fly as a receiver. Wireless video transmission technology suitable for mobile systems is divided into two parts: wireless communication technology and video coding technology. The most critical issue of the existing wireless video transmission technology for mobile applications is power consumption. But mobile devices have limited power source to meet high demand of power consumption. Practical solution is to reduce power consumption by wireless video transmission module in mobile devices.

The objective of the thesis is to design a new wireless video transmission technology as an alternative to the existing system that consists of popular standards IEEE 802.11 WLAN and H.264/MPEG. The proposed system will consume lower power and be of small size for mobile device while achieving high resolution video. We achieve the objective by using two approaches. The first is to reduce size and power of each module independently. The second is to combine video coder with wireless transceiver for efficient streaming of video from mobile to large displays. As a key technology for wireless communication, we selected features of the IEEEWPAN standards 802.15.3c utilizing 60 GHz single carrier modulation. It can support high resolution video with low power. As a video coding technology, we applied 3D-DCT (three-dimensional Discrete Cosine Transform). 3D-DCT takes very small area and less number of operations compared with H.264. Hence, it is expected to take low power as a single chip solution. These wireless communication and video coding modules are implemented efficiently in terms of hardware area and power. To implement the algorithms selected for the proposed system, proper specific VLSI architectures are selected or newly devised. In addition, both systems are combined together to reduce size and power and increase efficiency for a single chip solution.

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