Date of Award

6-2022

Document Type

Thesis

Publisher

Santa Clara : Santa Clara University, 2022.

Department

Electrical and Computer Engineering

First Advisor

Sara Tehranipoor

Second Advisor

Shoba Krishnan

Abstract

Developing and proving the effectiveness of ECG-based TRNGs for use in cryptography applications related to implantable medical devices (IMDs) offers a novel approach to securing IMDs. Current ECG-based True Random Number Generators (TRNGs) are software orientated and computationally heavy with hardware implementations being suggested as one possible solution to make such TRNGs useful for the medical device industry. Hardware offers the opportunity to increase power efficiency through algorithmic optimization while maintaining device security. In this paper, we use Verilog design and FPGA simulation tools to demonstrate the potential for hardware-accelerated ECG-based TRNGs for use in low power cryptographic applications. This is achieved by building an ECG-based TRNG with five functional blocks: noise extraction, storage of unique data, memory control, Lift and Shift, and data output. The Lift and Shift portion of the algorithm is the foundation of our TRNG and is critical to the operation and effectiveness of our solution through the use of a hash function, matrix mixer, and barrel shifters. Our experiments show that hardware implementations of ECG-based TRNGs are possible and practical with higher bit rate outputs than similar python-based solutions and the potential for desirable power efficiency. Further verification of our TRNGs randomness is to be completed with industry-accepted and national governing body-approved statistical test suites. We believe that an FPGA design allows for computational efficiency for ECG-based TRNGs when compared to software approaches while maintaining cryptographic security. This will be critical to ensuring IMD device security while maintaining the necessary ten-plus-year lifespan of such devices.

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