Date of Award

6-5-2026

Document Type

Thesis

Publisher

Santa Clara : Santa Clara University, 2026

Department

Computer Science and Engineering

First Advisor

Younghyun Cho

Abstract

Solving systems of linear equations is a core operation in high-performance computing and many scientific and engineering applications. One of the most widely used direct methods for solving such systems is LU factorization. Mixed-precision methods accelerate these solvers by using low-precision LU factorization with iterative refinement, improving performance and energy efficiency while preserving high numerical accuracy. AMD Accelerated Processing Units (APUs), which integrate CPU and NPU resources, provide an opportunity to explore this approach on emerging heterogeneous architectures. However, effective NPU utilization remains challenging due to workload partitioning, buffer management, data-movement overhead, and software tooling limitations.

This project implements a mixed-precision iterative solver on an AMD Ryzen AI 9 HX 370 APU system with Radeon 890M graphics, using collaborative CPU–NPU execution. BF16 and FP32 computations are used for performancecritical matrix operations, while FP64 residual computation and correction steps remain on the CPU for numerical reliability. Selected operations are offloaded to the NPU through Ryzen AI and MLIR-AIE, with CPU-side driver functions coordinating execution, data movement, and result integration.

Through profiling, evaluation, and tuning, this work demonstrates the feasibility of mixed-precision numerical solvers on CPU–NPU heterogeneous platforms and highlights practical limitations in current NPU hardware and software support.

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