Configurable HW/SW Co-design Partitioning Methodology
This dissertation investigates Hardware/Software co-design of systems for FPGA-based SoC boards. Hardware/Software co-design is a digital design approach that partitions system models into software executables, which typically run on CPUs, and synthesizable RTL, which is implemented on FPGAs. This implementation implies high speed, small footprints, and low power.
This research proposes a general HW/SW co-design methodology and shows that it can be algorithmically applied to identify practical hardware optimizations for the computationally-intensive components of systems. It demonstrates that systems partitioned efficiently can achieve orders of magnitude in terms of speedup, compared to a software-only implementation on a CPU. This architecture, based on HW/SW co-design, is reconfigurable for any target threshold or design constraint.
To demonstrate our methodology, we employ two use cases, namely Software-defined Radio (SDR) and Blockchain, and implement them on the Xilinx Zynq-7000 System-on- Chip (SoC), which was selected after conducting a comprehensive survey and analysis of all hardware alternatives. We study the soundness of our architectures with respect to various design parameters. We derive a cost evaluation mechanism to quickly and accurately assess the robustness of generated partitions and suggest various optimization procedures. Optimization decisions cover several aspects of partitions including communication, energy consumption, latency, and resource utilization. They aim to satisfy the system constraints. However, the search space is large due to the great number of possible combinations to optimize. We explore the automation of the decision-making process to minimize the search latency. Hence, we exploit the Binary Particle Swarm Optimization (BPSO) algorithm for systemic optimization and cost minimization. This partitioning algorithm is easy to implement in FPGA-based SoCs because of its methodical structure. Further, it can realize any high-level system model with the highest possible efficiency with minimum effort from developers.