Date of Award
Spring 2021
Document Type
Thesis
Publisher
Santa Clara : Santa Clara University, 2021.
Department
Electrical and Computer Engineering
First Advisor
Sara Tehranipoor
Abstract
Logic Locking is an emerging form of hardware obfuscation that is intended to be a solution to many of the trust issues associated with the modern globalized IC supply chain. By inserting extra key-gates into a circuit, the functionality of the circuit can be locked until the correct order of bits or “key” is applied to the key gates. To assess the strength of new logic locking techniques, we propose a new attack that uses deep reinforcement learning. This attack aims to test logic locking as well as evaluate reinforcement learning as a possible attack against logic locking. By using a deep Q-learning neural network, Q-values can be approximated and the model can be trained much faster than using traditional Q-learning. By allowing the model to change a single bit in the key each timestep, simulations of the circuit with the key produced can be run and the outputs can be compared to that of the unlocked version of the circuit, called an oracle. A reward is calculated based on how many bits of the locked circuit are correct and is used to reinforce the learning of the model. During the training phases of the model, the relationship between a highly correct key and how correct the outputs are for some random inputs is not strong, causing the model to struggle to learn quickly.
Recommended Citation
Shelton, Allen and Mellor, Jake, "Attacking Logic Locked Circuits Using Reinforcement Learning" (2021). Electrical and Computer Engineering Senior Theses. 58.
https://scholarcommons.scu.edu/elec_senior/58