Loop-Based Inductance Extraction and Modeling for Multiconductor On-Chip Interconnects
An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.
S. Yu, D.M. Petranovic, S. Krishnan, K. Lee, and C.Y. Yang, “Loop-Based Inductance Extraction and Modeling for Multiconductor On-Chip Interconnects,” IEEE Transactions on Electron Devices 53, 135-145 (2006).