Date of Award
Santa Clara : Santa Clara University, 2017.
This paper documents the investigation and implementation of the mathematics behind artificial intelligence using a programmable gate array interfaced through a software API. Machine learning is made possible through training on large amounts of information and is often performed across clusters of CPUs in an attempt to minimize runtime. In an attempt to make this process less resource intensive, we are researching how to optimize the most intensive of operations by offloading them to a field of programmable gate array.
Bernstein, Maor and Miller, Patrick, "Artificial Intelligence Hardware Accelerator" (2017). Computer Engineering Senior Theses. 98.