Date of Award


Document Type



Santa Clara : Santa Clara University, 2023.


Electrical and Computer Engineering

First Advisor

Andy Wolfe


The Cortex-M series is an immensely popular family of processors optimized for low cost, size, and power. The smallest of the M-family, the Cortex-M0, uses a 3-stage pipelined design. Despite their popularity, however, no publicly available open-source designs exist for the Cortex-M series. Thus, for our senior design project, we chose to create an open-source implementation of the Cortex-M0 processor in Verilog. This enables users to learn more about, experiment on, and make changes to the design of the processor.

Though our goal for this project was to support all the functionality of the Cortex-M0 processor (as defined in the instruction set architecture ARMv6-M), we were unable to do so in the limited timeframe of a senior design project due to various challenges encountered, although most functionality is supported and the design is able to execute assembly programs. As an open-source design, however, others who wish to improve and expand upon our project can easily do so.